Low Density Parity Code (LDPC) decoders are current generation iterative soft-input forward error correction (FEC) decoders that have found increasing popularity in FEC applications where low error floor and high performance are desired. LDPC decoders are defined in terms of a two-dimensional matrix, referred to as an H matrix, which describes the connections between the data and the parity. The H matrix comprises rows and columns of data and parity information. Decoding an LDPC code requires solving the LDPC code according to the H matrix based on a two-step iterative method. Soft-decoding the code causes convergence of the solved code with the true code; convergence is achieved over a number of iterations and results in a corrected code with no errors.
A category of LDPC codes, known as quasi-cyclic (QC) codes, generates an H matrix with features that improve the ease of implementing the LDPC encoder and decoder. In particular, it is possible to generate a QC-LDPC H matrix where some rows are orthogonal to each other. These orthogonal rows are treated as a layer, and rows within a layer can be processed in parallel, thus reducing the iterative cost of the decoder. It is advantageous to reduce the number of iterations necessary to decode an LDPC code.
LDPC codes typically have an error floor in terms of frame error rate (FER) performance as shown in FIG. 1. In the example shown in FIG. 1, the FER performance of the decoder follows ideal waterfall performance 10 until the error floor region of the code is approached. At this point, the real decoder performance 12 begins to diverge from ideal 10, eventually reaching a condition where the FER performance only improves slowly as the input BER is reduced.
Such error floors are caused by trapping sets where the decoder can no longer determine the correct solution method that will lead to eliminating the remaining errors even when given an infinite number of decode iterations. Such trapping sets are typically near code words containing a small number of errors compared to the real solution. A trapping set can be defined by a fixed number of failing check nodes, optionally plus or minus 1 in an oscillating pattern.
Error floors are present in most every LDPC code (or other code), even those employed in many communications standards. For many systems this error floor issue is accepted so long as the error floor of the H matrix used is below the requirement for the communication standard. For example, for a mobile wireless communication system, there are fading conditions that can periodically render a given link un-usable; such a communication system must be able to deal with high frame error rates and still be effective. In such a standard an error floor of 1e-5 would be acceptable, any losses at this point would not be noticed due to the inherent noise floor in the medium.
In the present disclosure, the error floor itself is defined as the FER at which the FER waterfall plot of the code diverges nearly horizontally from the ideal waterfall plot. Many communications standards have much lower error floor requirements, some at FER=1e-8 or FER=1e-10 and even lower. The difficulty of finding an H matrix exhibiting a given error floor increases exponentially with each decadal drop in the required error floor.
In some cases the exact trapping set or sets of a given H matrix can be dealt with using custom-built changes to the convergence methods of the decoder in question. Such custom methodic enhancements are expensive to generate, difficult to determine and ultimately only deal with a few of the trapping sets in any given H matrix.
Improvements in forward error correction approaches error floor mitigation are desirable.